#007 - Gdy bug w krzemie drzemie...
SPECIALE35- Survival Hacking - Elettronica personalizzata
Q&A#10 RAM Parallelism
Q&A#4 RAM Parallelism
#26-Ottimizzazione di moltiplicatori
ep#22-Multiplier optimization
Ep#21-Serial-to-Parallel Parallel-to-Serial converter
#25-Serial-to-Parallel e Parallel-to-Serial
Q&A#09-I need a clock!
Q&A#3 Alla ricerca del clock perduto
Q&A#2-cosa è il dithering
Q&A#08- What is the dithering
ep#20-VHDL Generic
Sveliamo il segreto: A cosa serve il VHDL
Ep#19-Iterative statement
Ep#18-the conditional assignment in VHDL
ep#17-wait
SPECIALE05 - Survival Hacking - Logiche Programmabili
Q&A#07- What is the first thing that a recruiter does?
Ep#16-VHDL process
Q&A#06- How can I generate a new clock from a reference clock?
Ep#15-VHDL Packages
Q&A#05- Does the USB transfer work as UART?
Ep#14-VHDL object
QA#04-What is the VHDL design flow
Ep#13-a way to remember-the flip-flop
QA#3-plzz send the test bench
Ep#12-VHDL Simulation
Ep#11-what is a signal
Ep#10-More on driver the resolution function
QA#2-SPI-controller-simulation with Vivado
QA#1-Do we need clock and address
Ep#08-concurrency
Ep#07-introducing the entity
Ep#06-Ok, and now how do I test it?
EP#04-Two is enough
Ep#03-a really important thing the interfaces
Ep#02-the three secrets that no hardware designer will ever tell you
Ep#01-Why you should learn VHDL
Ep#0-why a podcast on VHDL
#24-rendiamo parametriche le nostre entità
#23-per superare la monotonia
#22-ogni tanto bisogna scendere a compromessi
#21-Wait... fermiamoci
#20-Processi
#18-Oggetti in VHDL
#17-i segnali
#16-ancora sul concetto di driver
#15-il concetto di driver
#14-finalmente iniziamo a ricordare qualcosa il flip-flop
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