https://www.spreaker.com/show/five-minute-vhdl-podcastenTechnologyCopyright Francesco Richichihttps://d3wo5wojvuv7l.cloudfront.net/t_rss_itunes_square_1400/images.spreaker.com/original/d9e685a3ec101e4bed7a4cb0242a3a18.jpghttps://www.spreaker.com/show/five-minute-vhdl-podcastTue, 19 Mar 2024 10:23:27 +0000Francesco RichichiFrancesco Richichipodcast@surf-vhdl.comLet's talk about hardware design using VHDLfalse47b97134-d0fd-5ea4-bf79-f50e463937e8episodichttps://www.spreaker.com/episode/q-a-10-ram-parallelism--18010185
https://surf-vhdl.com/how-to-implement-a-multi-port-memory-on-fpga/


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https://surf-vhdl.link/courses]]>https://api.spreaker.com/episode/18010185Sat, 18 May 2019 16:53:59 +0000Francesco RichichiHow I can parallelize a RAM in FPGA https://surf-vhdl.com/how-to-implement-a-multi-port-memory-on-fpga/ Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram:...
https://surf-vhdl.com/how-to-implement-a-multi-port-memory-on-fpga/


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https://surf-vhdl.link/courses]]>220fpga,ram,vhdlfalse1fullhttps://www.spreaker.com/episode/ep-22-multiplier-optimization--17919050
For a technical analysis go to the post:

https://surf-vhdl.link/OptimizationVhdl12b25


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https://surf-vhdl.link/courses]]>https://api.spreaker.com/episode/17919050Mon, 13 May 2019 20:01:51 +0000Francesco RichichiLearn how to optimize a multiplier in particular cases: For a technical analysis go to the post: https://surf-vhdl.link/OptimizationVhdl12b25 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me...
For a technical analysis go to the post:

https://surf-vhdl.link/OptimizationVhdl12b25


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https://surf-vhdl.link/courses]]>323fpga,vhdlfalse1fullhttps://www.spreaker.com/episode/ep-21-serial-to-parallel-parallel-to-serial-converter--17726232https://surf-vhdl.link/99990


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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/17726232Sun, 28 Apr 2019 21:07:10 +0000Francesco RichichiLink to the post: https://surf-vhdl.link/99990 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram: https://t.me/francesco_surfvhdl Teachable courses...https://surf-vhdl.link/99990


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Music by Francis Preve - https://www.francispreve.com]]>444fpga,vhdlfalse1fullhttps://www.spreaker.com/episode/q-a-09-i-need-a-clock--17725896

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https://surf-vhdl.link/courses]]>https://api.spreaker.com/episode/17725896Tue, 23 Apr 2019 20:11:38 +0000Francesco RichichiIn this podcast we will understand how to connect a clock signal to our FPGA Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram:...

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https://surf-vhdl.link/courses]]>541clock,fpga,vhdl,xilinxfalse1fullhttps://www.spreaker.com/episode/q-a-08-what-is-the-dithering--17594838Where we can use this technique?

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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/17594838Wed, 10 Apr 2019 18:42:20 +0000Francesco RichichiWhat is dithering? Where we can use this technique? Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram: https://t.me/francesco_surfvhdl Teachable courses...Where we can use this technique?

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Music by Francis Preve - https://www.francispreve.com]]>270dithering,vhdlfalse1fullhttps://www.spreaker.com/episode/ep-20-vhdl-generic--17554343

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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/17554343Sat, 06 Apr 2019 15:16:38 +0000Francesco RichichiVHDL Generic Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram: https://t.me/francesco_surfvhdl Teachable courses https://surf-vhdl.link/courses Music...

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Music by Francis Preve - https://www.francispreve.com]]>334generic,vhdlfalse1fullhttps://www.spreaker.com/episode/ep-19-iterative-statement--17409438
https://t.me/SurfVhdl/92

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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/17409438Fri, 22 Mar 2019 22:02:11 +0000Francesco RichichiEven if the VHDL is not a software language, we can find a tyoica SW statement, the iterative statement. Let’s see how to use this https://t.me/SurfVhdl/92 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can...
https://t.me/SurfVhdl/92

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Music by Francis Preve - https://www.francispreve.com]]>283forloop,vhdlfalse1fullhttps://www.spreaker.com/episode/ep-18-the-conditional-assignment-in-vhdl--17363613image for the episode

http://t.me/SurfVhdl/86


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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/17363613Mon, 18 Mar 2019 21:29:37 +0000Francesco RichichiLet’s understand how to implement a conditional statement in VHDL image for the episode http://t.me/SurfVhdl/86 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com...image for the episode

http://t.me/SurfVhdl/86


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Music by Francis Preve - https://www.francispreve.com]]>448fpga,vhdlfalse1fullhttps://www.spreaker.com/episode/ep-17-wait--17314367Reference to pictures:

https://t.me/SurfVhdl/82


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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/17314367Wed, 13 Mar 2019 21:35:05 +0000Francesco RichichiWait Statements in VHDL Reference to pictures: https://t.me/SurfVhdl/82 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram:...Reference to pictures:

https://t.me/SurfVhdl/82


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Music by Francis Preve - https://www.francispreve.com]]>322fpga,vhdl,waitfalse1fullhttps://www.spreaker.com/episode/q-a-07-what-is-the-first-thing-that-a-recruiter-does--17257017When a recruiter needs to hire you as VHDL expert, what do you think he or she will do to understand if you are good for him or her?
What can you do in order to result a VHDL user?
Let’s see in this podcast.

Here you can find the feedback of my VHDL student

https://surf-vhdl.link/vhdl-student

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You can contact me
mail: podcast@surf-vhdl.com

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https://surf-vhdl.link/courses]]>https://api.spreaker.com/episode/17257017Thu, 07 Mar 2019 20:55:26 +0000Francesco RichichiQ&A#07- What is the first thing that a recruiter does? When a recruiter needs to hire you as VHDL expert, what do you think he or she will do to understand if you are good for him or her? What can you do in order to result a VHDL user? Let’s see in...When a recruiter needs to hire you as VHDL expert, what do you think he or she will do to understand if you are good for him or her?
What can you do in order to result a VHDL user?
Let’s see in this podcast.

Here you can find the feedback of my VHDL student

https://surf-vhdl.link/vhdl-student

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
https://t.me/francesco_surfvhdl

Teachable courses
https://surf-vhdl.link/courses]]>244fpga,vhdl,vhdljobfalse1fullhttps://www.spreaker.com/episode/ep-16-vhdl-process--17245196link to the images

https://t.me/SurfVhdl/78

Website
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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/17245196Wed, 06 Mar 2019 22:02:18 +0000Francesco RichichiAnd now is time to introduce formally a Process link to the images https://t.me/SurfVhdl/78 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram:...link to the images

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Music by Francis Preve - https://www.francispreve.com]]>437process,vhdlfalse1fullhttps://www.spreaker.com/episode/q-a-06-how-can-i-generate-a-new-clock-from-a-reference-clock--17196776
The question is:
“I want to generate Square of 999kHz, 1000kHz and 1001kHzin VHDL Language and that would be implemented on a Zynq ZC702 evaluation board.
Is it possible by using the DDS.? Can you provide your expertise and comment on it.”

Website
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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/17196776Fri, 01 Mar 2019 21:06:02 +0000Francesco RichichiI receiver a question from Sandip. He got my reference, from my post on DDS. The question is: “I want to generate Square of 999kHz, 1000kHz and 1001kHzin VHDL Language and that would be implemented on a Zynq ZC702 evaluation board. Is it possible...
The question is:
“I want to generate Square of 999kHz, 1000kHz and 1001kHzin VHDL Language and that would be implemented on a Zynq ZC702 evaluation board.
Is it possible by using the DDS.? Can you provide your expertise and comment on it.”

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

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Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com]]>638clock,fpga,nco,vhdl,xilinxfalse1fullhttps://www.spreaker.com/episode/ep-15-vhdl-packages--17045730
http://t.me/SurfVhdl/74

Website
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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/17045730Thu, 14 Feb 2019 21:00:47 +0000Francesco RichichiVHDL Packages http://t.me/SurfVhdl/74 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram: https://t.me/francesco_surfvhdl Teachable courses...
http://t.me/SurfVhdl/74

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mail: podcast@surf-vhdl.com

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Music by Francis Preve - https://www.francispreve.com]]>231fpga,packages,vhdlfalse1fullhttps://www.spreaker.com/episode/ep-14-vhdl-object--16997718
Images
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mail: podcast@surf-vhdl.com

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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/16997718Mon, 11 Feb 2019 21:09:07 +0000Francesco RichichiAfter signal introduction, let's view what are the remaining VHDL objects Images https://t.me/SurfVhdl/72 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram:...
Images
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mail: podcast@surf-vhdl.com

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Music by Francis Preve - https://www.francispreve.com]]>371fpga,vhdlfalse1fullhttps://www.spreaker.com/episode/q-a-05-does-the-usb-transfer-work-as-uart--17004453Haitham is following my VHDL course “Start Learning VHDL Using FPGA”. In this course the last LAB implement communication between PC and FPGA using UART channel.
After starting the course, Haitham asked me: “Does the USB transfer work as UART”?
Let’s see the answer. Here the link to the picture on the telegram channel

https://t.me/SurfVhdl/68

Website
https://surf-vhdl.com

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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/17004453Sun, 10 Feb 2019 20:34:54 +0000Francesco RichichiI received a question from Haitham. He have to connect a computer to an FPGA using USB connection in order to transfer data from FPGA to the PC. Haitham is following my VHDL course “Start Learning VHDL Using FPGA”. In this course the last LAB...Haitham is following my VHDL course “Start Learning VHDL Using FPGA”. In this course the last LAB implement communication between PC and FPGA using UART channel.
After starting the course, Haitham asked me: “Does the USB transfer work as UART”?
Let’s see the answer. Here the link to the picture on the telegram channel

https://t.me/SurfVhdl/68

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

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Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com]]>555fpga,uart,usb,vhdlfalse1fullhttps://www.spreaker.com/episode/qa-04-what-is-the-vhdl-design-flow--16989968To better follow the episode, see the picture on the telegram channel

https://t.me/SurfVhdl/65

Website
https://surf-vhdl.com

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https://t.me/SurfVhdl

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mail: podcast@surf-vhdl.com

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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/16989968Fri, 08 Feb 2019 22:04:37 +0000Francesco RichichiIn this Q&A episode I want to answer to the question on what is the VHLD design flow To better follow the episode, see the picture on the telegram channel https://t.me/SurfVhdl/65 Website https://surf-vhdl.com Telegram channel...To better follow the episode, see the picture on the telegram channel

https://t.me/SurfVhdl/65

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

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Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com]]>429altera,fpga,vhdl,xilinxfalse1fullhttps://www.spreaker.com/episode/ep-13-a-way-to-remember-the-flip-flop--16978707
Link to the picture in the telegram channel

https://t.me/SurfVhdl/61

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/16978707Thu, 07 Feb 2019 20:50:34 +0000Francesco RichichiIntroducing Flip-Flop in VHDL Link to the picture in the telegram channel https://t.me/SurfVhdl/61 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram:...
Link to the picture in the telegram channel

https://t.me/SurfVhdl/61

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

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Music by Francis Preve - https://www.francispreve.com]]>341flipflop,fpga,vhdlfalse1fullhttps://www.spreaker.com/episode/qa-3-plzz-send-the-test-bench--16959669I wish to give you some hint and a test bench template I use in my VHDL designs

Here the link to the test bench template: https://t.me/SurfVhdl/58

Website
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mail: podcast@surf-vhdl.com

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Teachable courses
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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/16959669Tue, 05 Feb 2019 21:03:47 +0000Francesco RichichiThis is the question many of you ask me very often I wish to give you some hint and a test bench template I use in my VHDL designs Here the link to the test bench template: https://t.me/SurfVhdl/58 Website https://surf-vhdl.com Telegram...I wish to give you some hint and a test bench template I use in my VHDL designs

Here the link to the test bench template: https://t.me/SurfVhdl/58

Website
https://surf-vhdl.com

Telegram channel
https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

Telegram:
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Teachable courses
https://surf-vhdl.link/courses

Music by Francis Preve - https://www.francispreve.com]]>220fpga,testbench,vhdlfalse1fullhttps://www.spreaker.com/episode/ep-12-vhdl-simulation--16940776Link to the episode#12 picture
t.me/SurfVhdl/53

Website
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mail: podcast@surf-vhdl.com

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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/16940776Sun, 03 Feb 2019 21:31:56 +0000Francesco RichichiA brief overview to setup a ModelSim simulation environment Link to the episode#12 picture t.me/SurfVhdl/53 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram:...Link to the episode#12 picture
t.me/SurfVhdl/53

Website
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https://t.me/SurfVhdl

You can contact me
mail: podcast@surf-vhdl.com

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Teachable courses
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Music by Francis Preve - https://www.francispreve.com]]>351fpga,vhdlfalse1fullhttps://www.spreaker.com/episode/ep-11-what-is-a-signal--16925821
Image relative to this episode


Website
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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/16925821Fri, 01 Feb 2019 21:42:12 +0000Francesco RichichiIntroduce signal in VHDL, what is a signal and how to use it. Image relative to this episode Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram:...
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Music by Francis Preve - https://www.francispreve.com]]>233fpga,vhdlfalse1fullhttps://www.spreaker.com/episode/ep-10-more-on-driver-the-resolution-function--16885892
Link to image for the episode#10
Solving a dispute in VHDL: the resolution function

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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/16885892Wed, 30 Jan 2019 18:13:54 +0000Francesco RichichiSolving a dispute in VHDL: the resolution function Link to image for the episode#10 Solving a dispute in VHDL: the resolution function t.me/SurfVhdl/50 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can...
Link to image for the episode#10
Solving a dispute in VHDL: the resolution function

t.me/SurfVhdl/50

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Music by Francis Preve - https://www.francispreve.com]]>493fpga,vhdlfalse1fullhttps://www.spreaker.com/episode/ep-09-what-is-a-driver-in-vhdl--16877550
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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/16877550Tue, 29 Jan 2019 21:24:15 +0000Francesco RichichiWhat is a driver in VHDL? Images for the episode t.me/SurfVhdl/46 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram: https://t.me/francesco_surfvhdl...
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Music by Francis Preve - https://www.francispreve.com]]>237false1fullhttps://www.spreaker.com/episode/qa-2-spi-controller-simulation-with-vivado--16864739
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https://surf-vhdl.link/courses]]>https://api.spreaker.com/episode/16864739Mon, 28 Jan 2019 18:40:03 +0000Francesco RichichiIn this brief episode I want to answer a question from Klajdi on simulation of SPI controller using Vivado Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram:...
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https://surf-vhdl.link/courses]]>123fpga,vhdl,vivado,xilinxfalse1fullhttps://www.spreaker.com/episode/qa-1-do-we-need-clock-and-address--16849528
“What do we have to give as an input for i_clk and i_addr?”

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Music by Francis Preve - https://www.francispreve.com/]]>https://api.spreaker.com/episode/16849528Sat, 26 Jan 2019 17:28:35 +0000Francesco RichichiAnswering to Prashant. He asked me this question “What do we have to give as an input for i_clk and i_addr?” relative to the post: https://surf-vhdl.com/how-to-generate-sine-samples-in-vhdl/ Website https://surf-vhdl.com Telegram...
“What do we have to give as an input for i_clk and i_addr?”

relative to the post:

https://surf-vhdl.com/how-to-generate-sine-samples-in-vhdl/

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Music by Francis Preve - https://www.francispreve.com/]]>235dds,fpga,vhdlfalse1fullhttps://www.spreaker.com/episode/ep-08-concurrency--16843899
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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/16843899Fri, 25 Jan 2019 22:56:34 +0000Francesco RichichiIn this episode we will introduce the Concurrency concept Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram: https://t.me/francesco_surfvhdl Teachable...
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Music by Francis Preve - https://www.francispreve.com]]>396fpga,vhdlfalse1fullhttps://www.spreaker.com/episode/ep-07-introducing-the-entity--16815155
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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/16815155Tue, 22 Jan 2019 21:29:22 +0000Francesco RichichiIntroducing Entity. The basic building VHDL block Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram: https://t.me/francesco_surfvhdl Teachable courses...
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Music by Francis Preve - https://www.francispreve.com]]>593fpga,vhdlfalse1fullhttps://www.spreaker.com/episode/ep-06-ok-and-now-how-do-i-test-it--16758131
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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/16758131Sat, 19 Jan 2019 22:43:07 +0000Francesco RichichiLet’s understand how digital electronics help us in the debug and test of our design Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram:...
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Music by Francis Preve - https://www.francispreve.com]]>276fpga,vhdlfalse1fullhttps://www.spreaker.com/episode/ep-05-male-and-female-logic--16751526
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Music by Francis Preve - https://www.francispreve.com/]]>https://api.spreaker.com/episode/16751526Fri, 18 Jan 2019 22:44:12 +0000Francesco RichichiLearn how men and women can be identified as digital circuits Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram: https://t.me/francesco_surfvhdl Teachable...
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Music by Francis Preve - https://www.francispreve.com/]]>257false1fullhttps://www.spreaker.com/episode/ep-04-two-is-enough--16722078
Figures:

https://t.me/SurfVhdl/32


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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/16722078Tue, 15 Jan 2019 20:40:03 +0000Francesco RichichiWhy do we use only two logic level in digital design? Figures: https://t.me/SurfVhdl/32 Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram:...
Figures:

https://t.me/SurfVhdl/32


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Music by Francis Preve - https://www.francispreve.com]]>386fpga,vhdlfalse1fullhttps://www.spreaker.com/episode/ep-03-a-really-important-thing-the-interfaces--16694885
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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/16694885Tue, 15 Jan 2019 06:00:06 +0000Francesco RichichiLet's introduce the FLAT and Hierarchical methodology in Hardware Design Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram: https://t.me/francesco_surfvhdl...
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Music by Francis Preve - https://www.francispreve.com]]>281fpga,vhdlfalse1fullhttps://www.spreaker.com/episode/ep-02-the-three-secrets-that-no-hardware-designer-will-ever-tell-you--16694811
Website
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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/16694811Mon, 14 Jan 2019 06:00:07 +0000Francesco RichichiStart understanding few rules for a good VHDL design habits Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram: https://t.me/francesco_surfvhdl Teachable...
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Music by Francis Preve - https://www.francispreve.com]]>309fpga,vhdlfalse1fullhttps://www.spreaker.com/episode/ep-01-why-you-should-learn-vhdl--16694802Why you should learn VHDL?
Let's understand in this episode

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Music by Francis Preve - https://www.francispreve.com]]>https://api.spreaker.com/episode/16694802Sun, 13 Jan 2019 06:00:13 +0000Francesco RichichiDo you like digital electronic? Why you should learn VHDL? Let's understand in this episode Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram:...Why you should learn VHDL?
Let's understand in this episode

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Music by Francis Preve - https://www.francispreve.com]]>321fpga,vhdlfalse1fullhttps://www.spreaker.com/episode/ep-0-why-a-podcast-on-vhdl--16694466Five Minute VHDL

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Music by Francis Preve - https://www.francispreve.com/]]>https://api.spreaker.com/episode/16694466Sat, 12 Jan 2019 15:11:02 +0000Francesco RichichiEpisode zero to introduce the Surf-VHDL Podcast: Five Minute VHDL Website https://surf-vhdl.com Telegram channel https://t.me/SurfVhdl You can contact me mail: podcast@surf-vhdl.com Telegram: https://t.me/francesco_surfvhdl...Five Minute VHDL

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Music by Francis Preve - https://www.francispreve.com/]]>281fpga,vhdlfalse1full